1. Field of the Invention
The present invention relates to a system LSI in which a CPU (central processing unit) and various types of controllers are brought together as a single LSI (large scale integrated circuit), and which can structure a microcomputer by being connected to an external memory.
2. Description of the Related Art
FIG. 2 is a structural diagram showing the basics of a conventional system LSI (which is also called a microcontroller)
A system LSI 10 accesses external devices such as a ROM (read-only memory) 1, a RAM (a memory to which data can be written and from which data can be read as occasion demands) 2, an input/output device (IO) 3, or the like, and has a CPU 11 which carries out overall computation and control on the basis of programs stored in the ROM 1. The CPU 11 is connected to an access control register 13 and an external bus controller 14 via a bus interface 12 (hereinafter called “bus I/F”).
The bus I/F 12 serves as an intermediary at the time when the CPU 11 carries out writing and reading with respect to the access control register 13. A control signal CON, for controlling various types of operations, is supplied from the CPU 11 to the bus I/F 12. A ready signal RDY, which expresses whether or not preparations have been completed, and read data RDT are supplied from the bus I/F 12 to the CPU 11.
The access control register 13 holds data which has been supplied as write data WDT from the CPU 11 via the bus I/F 12, and functions to transfer the held data as an access cycle value CYC to the external bus controller 14.
Moreover, the bus I/F 12 has a decoder 12a which has the function of supplying, on the basis of the control signal CON supplied from the CPU 11 and as request signals ROMRQ, RAMRQ, IORQ and to the external bus controller 14, information expressing which external device (i.e., the ROM 1, the RAM 2, or the input/output device 3) is desired to be accessed.
When a request signal is supplied from the bus I/F 12, the external bus controller 14 carries out a reading or writing access operation with respect to the external device requested in the request signal, at an access cycle corresponding to the access cycle value CYC transferred from the access control register 13.
Selection signals CS1, CS2, CS3, which are from the external bus controller 14 and are for the ROM 1, the RAM 2 and the input/output device 3, are outputted to external terminals 15a, 15b, 15c, respectively. Moreover, an external address signal EXAD, which designates the region which is the object of reading or writing in the ROM 1 or the like which is selected, and an external bus read signal EXRD, which is for carrying out a read request, are outputted to external terminals 16, 17, respectively. On the other hand, external data EXDT, which has been read and outputted from the selected external memory, is supplied to the external bus controller 14 via an external terminal 18.
Moreover, in order for the external data EXDT, which has been outputted from a low-speed external device such as the input/output device 3, to be inputted without errors to the external bus controller 14, a wait signal XWAIT outputted from the input/output device 3 is supplied to the external bus controller 14 via an external terminal 19. The system LSI 10 operates synchronously with a clock signal CLK supplied from the exterior to a clock terminal 20.
In such a system LSI 10, operation is started by connecting the ROM 1, in which programs for processing control are stored in advance, and the RAM 2, which has a predetermined storage capacity, and the requisite input/output device 3, to the external terminals 15–19, and by the clock signal CLK of a predetermined frequency being supplied to the clock terminal 20 from the exterior.
Immediately after the start of operation, the maximum access cycle value CYC is held as an initial value in the access control register 13. In this way, thereafter, when the external bus controller 14 reads out an initial program from an external memory such as the ROM 1 or the RAM 2, access is carried out on the basis of this access cycle value CYC. Namely, after a read request has been carried out, an initialization program can be read out without errors by carrying out reading of the external data EXDT at the point in time when the clock number corresponding to the access cycle value CYC has been reached.
However, the system LSI has the following problems.
In a case in which, for example, a testing device is connected to the external terminals 15–19 and the clock terminal 20 of the system LSI 10 and is operated at a clock signal CLK which is higher-speed than that at the time of usual operation, even if the access cycle value CYC of the access control register 13 is set to the maximum value, there are cases in which, due to the effects of the drive circuits of the external terminals 15–19, the external data EXDT does not follow the clock signal CLK, the correct data cannot be read, and high-speed testing cannot be carried out.